This invention relates to a semiconductor memory device (hereinbelow, simply termed "memory"), and more particularly to a static type semiconductor random access memory (hereinbelow, abbreviated to "static RAM").
In a static RAM, a pair of information signals complementary to each other which are derived from a memory cell are respectively transmitted to a sense amplifier through a pair of data lines and pair of common data lines CDL and CDL. The sense amplifier amplifies the potential difference between the pair of common data lines having developed in accordance with the pair of information signals, and transmits the output signal of high level or low level to a data output buffer. The data output buffer detects on the basis of its ligic threshold voltage whether the output signal from the sense amplifier is the high level or the low level, and it delivers the output data of the high level or the low level out of the static RAM in accordance with the detected result.
In "NIKKEI ELECTRONICS 1980. 3. 7.", page 142, FIG. 12, by YASUI et al., it has been proposed and illustrated to employ as the aforementioned sense amplifier a differential amplifier circuit which is constructed of a pair of insulated gate field effect transistors (hereinbelow, termed "MISFETs") coupled in the differential mode, and a current mirror circuit (active load) forming the load of the MISFETs. In this sense amplifier, the output signal is formed on the basis of current equal to the difference between the drain currents of the pair of MISFETs coupled in the differential mode. Therefore, the sensitivity of this sense amplifier can be made comparatively high. Moreover, since the load constituting the differential amplifier circuit is an active load, the gain of the differential amplifier circuit itself can also be made comparatively great, for example, about 5. In order to render the operation of the static RAM faster, however, a sense amplifier having a still higher gain is desired for reasons set forth in the following discussion.
To begin with, since the pair of data lines has a large number of memory cells coupled thereto, the data lines have comparatively large parasitic capacitances. Further, in a static RAM of enlarged memory capacity, the common data lines become relatively long. Thus, the common data lines also have comparatively large storage capacitances. Therefore, when the information of the memory cell is read out, potential changes to be applied to the pair of data lines by the memory cell have their changing rates limited by the parasitic capacitances. Similarly, potential changes to be applied from the pair of data lines to the pair of common data lines are limited by the storage capacitances of the latter. In other words, the potential difference which is applied between the pair of common data lines in accordance with the information read out from the memory cell does not increase rapidly. To the contrary, the increase is relatively low.
Although the sense amplifier referred to above has a comparatively great gain, this gain is still unsatisfactory for the sense amplifier of the large-capacity static RAM. Therefore, when the potential difference between the pair of common data lines has become a comparatively great value, an output signal capable of driving the data output buffer is first provided form the sense amplifier. A comparatively long time is accordingly required before the data output buffer comes into operation after the information signals complementary to each other have been delivered from the memory cell to the pair of data lines.
Moreover, in the foregoing sense amplifier, the differential amplifier circuit is constructed as a dissymmetric type differential amplifier circuit. This is a type of differential amplifier which receives a pair of input signals complementary to each other and which forms a single output signal having a potential relative to the ground potential of the circuitry which corresponds to the potential difference between the input signals. In consequence, the data output buffer detects the potential of the output signal from the sense amplifier on the basis of its logic threshold voltage relative to the ground potential of the circuitry. In this regard, however, the characteristics of elements constituting the data output buffer vary due to the variations of manufacturing conditions, etc. The variation of the characteristics of the elements results in the variation of the logic threshold voltages of data output buffers. In order to prevent any malfunction of the static RAM attributed to such variation of the logic threshold voltage of the data output buffer, the sense amplifier should desirably form an output signal of the largest possible amplitude. Since, however, the gain of the foregoing sense amplifier is not very high, the potential difference between the pair of common data lines must be still greater to the end of forming the output signal of the large amplitude. Therefore, an even longer time is taken before the data output buffer is operated. The operating speed of the static RAM has accordingly been greatly limited by these problems.
In addition, the characteristics of elements constituting the sense amplifier vary due to the variations of manufacturing conditions, etc. This can result in the sense amplifier having an offset. The sense amplifier is accordingly disadvantageous in that an offset voltage caused by the offset is transmitted to the data output buffer as it is.
For the above reasons, when the foregoing type of sense amplifier is employed, the output buffer cannot be driven by the sense amplifier until the potential difference between the pair of common data lines CDL and CDL reaches such a comparatively great value as 0.5 volt. This has formed a serious obstacle to achieving the high-speed operation of the static RAM.